Circuit depth defines the current Heron boundary.

The primary sequential evidence is split across an 8-step run on IBM Kingston and a 12-step run on IBM Fez. Heron R3 processors Pittsburgh and Boston are used for supporting transfer checks, including same-backend trajectories and a Boston-to-Pittsburgh continuation.

This division matters. A transfer check asks whether the unit cell survives a new hardware context. The four-state and synthesis rows ask a different, exploratory scaling question; neither replaces the primary campaign or creates a cross-device guarantee.

The optimized four-state circuit reports six of six cases below the paper's strict Hellinger corridor. This extends the exploratory operating map from the two-qubit Tiger unit cell to a shallow three-qubit encoding.

The result is useful because it separates a modest increase in state-space size from a major increase in compiled depth. It remains an exploratory pilot, not evidence of a realistic large-state autonomous system.

In the deeper four-state stress envelope, three of six cases pass the strict band while five of six preserve the maximum-a-posteriori state. UCGate and QSD pilots continue the same probe with richer compiled chains.

The paper's conclusion is direct: current Heron processors are constrained first by circuit depth per belief update. When the oracle remains shallow, the posterior can remain stable; when compilation produces a deep chain, the result marks the coherence frontier instead of a validated operating corridor.

The paper treats layerwise Richardson extrapolation, bounded zero-noise extrapolation, gate twirling, and adaptive barrier FPAA as diagnostics. Gate twirling can help in the shallow Tiger and four-state corridor, while its overhead becomes counterproductive on deeper UCGate chains.

This is why a single mitigation recipe would be misleading. The correct choice depends on the compiled circuit, backend, depth, and calibration state. Mitigation cannot be assumed to rescue a circuit that is already outside the coherence envelope.

Primary evidence remains the 8-step Kingston and 12-step Fez sequential Tiger posteriors. Heron R3 transfer rows are supporting controls. The optimized and deeper four-state rows, plus UCGate and QSD runs, remain exploratory evidence that localizes the bottleneck.

The paper excludes wall-clock speedup, hardware advantage, full policy optimization, end-to-end autonomy, and downstream MTDA advantage. The classical tractability of the small Tiger cell is also explicit, so the scale-up pilots cannot be read as a performance win over classical planning.

The practical roadmap is to reduce problem-specific oracle depth, preserve transpile manifests, test the same posterior and action gates, and collect reliable queue-inclusive and queue-exclusive timing fields on future live-hardware reruns. Only then can runtime cost be discussed responsibly.

A QANTIS evidence packet should therefore include backend, circuit source, compiled depth, two-qubit gate count, shots, calibration window, mitigation choice, raw counts, posterior metrics, and fallback state. Scale is credible only when all of those remain inspectable.

A larger state space does not translate into one fixed hardware cost. The encoding determines how many operations the processor must preserve before measurement, so two problems with the same number of states can occupy very different physical regimes after transpilation.

The QANTIS controls use a shallow 4-state corridor and deeper UCGate pilots to separate these effects. Shallow two- and three-qubit belief oracles can be stabilized in the reported corridor; deeper compiled chains become coherence-limited. The evidence therefore identifies circuit depth per update as the current binding constraint.

That is a useful negative boundary. It tells an engineering team to invest in shallower, problem-specific belief encodings and to preserve the classical decision path while waiting for better hardware. It does not justify turning exploratory pilots into a production-readiness or quantum-advantage claim.

arXiv:2607.06760, submitted 7 July 2026, explicitly separates its primary Tiger result, supporting controls, and exploratory 4-state and UCGate scaling evidence. The paper describes the deeper runs as an operating-boundary probe for present IBM Heron hardware.

This article preserves that hierarchy. Heron is the tested processor family, not proof of a hardware advantage; the larger encodings map where current depth becomes limiting, not where general autonomous-system readiness begins.